Course Goals |
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ASIC vs FPGA vs CPU, HDL vs Schematic, Verilog language, Data Flow Graphs, RTL design, timing optimization, area optimization, synthesis, verification, capturing functional and timing specs from a loose design problem, deciding if an FPGA is the right choice, designing electronic systems around FPGAs, lab work on specific designs such as Calculator, Seven Segment driver, Mouse driver, VGA driver, a simple CPU. In the process of taking this course, describe how digital circuits are implemented, Data Flow Graphs, Timing Constraints, Speed-Area- Power trade-offs as well as the trade-off between using FPGAs and regular CPUs. |